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256-position i 2 c compatible digital potentiometer ad5245 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 256-position end-to-end resistance 5 k?, 10 k?, 50 k?, 100 k? compact sot-23-8 (2.9 mm 3 mm) package fast settling time: t s = 5 s typ on power-up full read/write of wiper register power-on preset to midscale extra package address decode pin ad0 computer software replaces c in factory programming applications single supply: 2.7 v to 5.5 v low temperature coefficient 45 ppm/c low power, i dd = 8 a wide operating temperature C40c to +125c evaluation board available applications mechanical potentiometer replacement in new designs lcd panel v com adjustment lcd panel brightness and contrast control transducer adjustment of pressure, temperature, position chemical, and optical sensors rf amplifier biasing automotive electronics adjustment gain control and offset adjustment general overview the ad5245 provides a compact 2.9 mm 3 mm packaged solution for 256-position adjustment applications. these devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. the wiper settings are controllable through an i 2 c compatible digital interface, which can also be used to read back the wiper register content. ad0 can be used to place up to two devices on the same bus. command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption. functional block diagram i 2 c interface wiper register scl s d a ad0 gnd v dd a w b 03436-a-001 por figure 1. pin configuration a b ad0 sda 1 2 3 4 5 8 7 6 w v dd gnd scl top view (not to scale) ad5245 03436-a-002 figure 2. operating from a 2.7 v to 5.5 v power supply and consuming less than 8 a allows for usage in portable battery-operated applications. note that the terms digital potentiometer, vr, and rdac are used interchangeably.
ad5245 rev. a | page 2 of 20 table of contents electrical characteristics5 k ? version ...................................... 3 electrical characteristics10 k ? , 50 k ? , 100 k ? versions ....... 4 timing characteristics5 k ? , 10 k ? , 50 k ? , 100 k ? versions 5 absolute maximum ratings............................................................ 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 test circuits..................................................................................... 12 theory of operation ...................................................................... 13 programming the variable resistor ......................................... 13 programming the potentiometer divider ............................... 14 esd protection ........................................................................... 14 terminal voltage operating range.......................................... 14 power-up sequence ................................................................... 14 layout and power supply bypassing ....................................... 15 constant bias to retain resistance setting............................. 15 evaluation board ........................................................................ 15 i 2 c interface..................................................................................... 16 i 2 c compatible 2-wire serial bus............................................ 16 outline dimensions ....................................................................... 19 ordering guide........................................................................... 19 revision history 3/04changed data sheet from rev. 0 to rev. a updated format.................................................................universal changes to features ........................................................................ 1 changes to applications ................................................................. 1 changes to figure 1......................................................................... 1 changes to electrical characteristics5 k? version ................ 3 changes to electrical characteristics10 k?, 50 k?, and 100 k? versions ....................................................................... 4 changes to timing characteristics.............................................. 5 changes to absolute maximum ratings ...................................... 6 moved esd caution to page.......................................................... 6 changes to and moved pin configuration and function descriptions to page........................................................................ 7 changes to figures 22 and 23 ...................................................... 11 moved figure 25 to figure 26 ...................................................... 11 moved figure 26 to figure 27 ...................................................... 11 moved figure 27 to figure 25 ...................................................... 11 deleted figures 31 and 32 ............................................................ 12 changes to figure 32, figure 33 and figure 34 ......................... 12 changes to rheostat operation section .................................... 13 added figure 35 ............................................................................ 13 changes to equation 1 and equation 2 ...................................... 13 changes to table 6 and table 7 ................................................... 13 added figure 37 ............................................................................ 14 changes to equation 4 .................................................................. 14 deleted readback rdac value section..................................... 14 deleted level shifting for bidirectional interface section ...... 14 moved esd protection section to page ..................................... 14 changes to figure 38 and figure 39............................................ 14 moved terminal voltage operating range section to page.... 14 changes to figure 40..................................................................... 14 moved power-up sequence section to page ............................. 14 moved layout and power supply bypassing section to page . 15 added constant bias to retain resistance setting section..... 15 added figure 42 ............................................................................ 15 added evaluation board section ................................................ 15 added figure 43 ............................................................................ 15 moved i 2 c interface section to page........................................... 16 changes to and moved i2c compatible 2-wire serial bus section to page............................................................................... 16 moved table 5 and table 6 to page ............................................. 17 (renumbered as table 8 and table 9) moved figure 36, figure 37, and figure 38 to page .................. 17 (renumbered as figure 44, figure 45, and figure 46) moved multiply devices on one bus section to page ............. 18 updated ordering guide.............................................................. 19 updated outline dimensions...................................................... 19 moved i 2 c disclaimer to page ..................................................... 20 5/03revision 0: initial version
ad5245 rev. a | page 3 of 20 electrical characteristics5 k? version v dd = 5 v 10%, or 3 v 10%; v a = +v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C4 0.75 +4 lsb nominal resistor tolerance 3 ?r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w 50 120 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C1.5 0.6 +1.5 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C6 C2.5 0 lsb zero-scale error v wzse code = 0x00 0 +2 +6 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 90 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 95 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 44 w power supply sensitivity pss v dd = +5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6, 9 bandwidth C3 db bw_5k r ab = 5 k?, code = 0x80 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 2.5 k?, r s = 0 6 nv/hz 1 typical specifications represent average readings at +25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. va = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum ar e guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polari ty with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v.
ad5245 rev. a | page 4 of 20 electrical characteristics10 k?, 50 k?, 100 k? versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect C1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect C2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab t a = 25c C30 +30 % resistance temperature coefficient (?r ab /r ab )/?t 10 6 v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w v dd = 5 v 50 120 ? dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl C1 0.1 +1 lsb integral nonlinearity 4 inl C1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t 10 6 code = 0x80 15 ppm/c full-scale error v wfse code = 0xff C3 C1 0 lsb zero-scale error v wzse code = 0x00 0 1 3 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance 6 a, b c a , c b f = 1 mhz, measured to gnd, code = 0x80 90 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 95 pf shutdown supply current i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 7 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 44 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6, 8 bandwidth C3 db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 600/100/40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, r s = 0 9 nv/hz 1 typical specifications represent average readings at +25c and v dd = 5 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured betw een the maximum re sistance and th e minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. va = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w ha ve no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 8 all dynamic characteristics use v dd = 5 v.
ad5245 rev. a | page 5 of 20 timing characteristics5 k?, 10 k?, 50 k?, 100 k? versions v dd = 5v 10%, or 3v 10%; v a = v dd ; v b = 0 v; C40c < t a < +125c; unless otherwise noted. table 3. parameter symbol conditions min typ 1 max unit i 2 c interface timing characteristics 2, 3 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s 1 typical specifications represent average readings at +25c and v dd = 5 v. 2 guaranteed by design and not subject to production test. 3 see timing diagrams for lo cations of measured values.
ad5245 rev. a | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter value v dd to gnd C0.3 v to +7 v v a , v b , v w to gnd v dd terminal current, a to b, a to w, b to w 1 pulsed 20 ma continuous 5 ma digital inputs and output vo ltage to gnd 0 v to +7 v operating temperature range C40c to +125c maximum junction temperature (t jmax ) 150c storage temperature C65c to +150c lead temperature (soldering, 10 sec) 245c thermal resistance 2 ja : sot-23-8 230c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5245 rev. a | page 7 of 20 pin configuration and fu nction descriptions a b ad0 sda 1 2 3 4 5 8 7 6 w v dd gnd scl top view (not to scale) ad5245 03436-a-002 figure 3. pin configuration table 5. pin function descriptions pin name description 1 w w terminal. gnd v w v dd. 2 v dd positive power supply. 3 gnd digital ground. 4 scl serial clock input. positive edge triggered. pull-up resistor rquired. 5 sda serial data input/output. pull-up resistor required. 6 ad0 programmable address bit 0 for two-device decoding. 7 b b terminal. gnd v b v dd. 8 a a terminal. gnd v a v dd.
ad5245 rev. a | page 8 of 20 typical performance characteristics code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 32 096 64 128 160 192 224 256 rheostat mode inl (lsb) 0.8 5v 3v 03436-a-003 figure 4. r-inl vs. code vs. supply voltages 5v 3v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode dnl (lsb) 0.8 code (decimal) 32 096 64 128 160 192 224 256 03436-a-004 figure 5. r-dnl vs. code vs. supply voltages _ 40c +25c +85c +125c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 potentiometer mode inl (lsb) 0.8 code (decimal) 32 096 64 128 160 192 224 256 03436-a-005 figure 6. inl vs. code vs. temperature , v dd = 5 v code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 32 096 64 128 160 192 224 256 potentiometer mode dnl (lsb) 0.8 ?40c +25c +85c +125c 03436-a-006 figure 7. dnl vs. code vs. temperature, v dd = 5 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 potentiometer mode inl (lsb) 0.8 code (decimal) 32 096 64 128 160 192 224 256 5v 3v 03436-a-007 figure 8. inl vs. code vs. supply voltages 5v 3v code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 32 096 64 128 160 192 224 256 potentiometer mode dnl(lsb) 1.0 03436-a-008 figure 9. dnl vs. code vs. supply voltages
ad5245 rev. a | page 9 of 20 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode inl (lsb) 0.8 code (decimal) 32 096 64 128 160 192 224 256 c +25c +85c +125c ?40 03436-a-009 figure 10. r-inl vs. code vs. temperature, v dd = 5 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode dnl (lsb) 0.8 code (decimal) 32 096 64 128 160 192 224 256 _ 40c +25c +85c +125c 03436-a-010 figure 11. r-dnl vs. code vs. temperature, v dd = 5 v temperature (c) 0 40 80 120 ?40 0 1.5 fse, full-scale error (lsb) 0 40 80 120 ?40 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 03436-a-011 figure 12. full-scale error vs. temperature 0 40 80 120 ?40 0 1.5 zse, zero-scale error ( a) temperature (c) 0 40 80 120 ?40 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 03436-a-012 figure 13. zero-scale error vs. temperature temperature (c) 0 40 80 120 ?40 0.1 1 10 i dd supply current ( a) v dd = 5.5v v dd = 2.7v 03436-a-013 figure 14. supply current vs. temperature i a shutdown current (na) temperature (c) 0 0 70 20 10 30 40 50 60 40 80 120 ?40 v dd = 5v 03436-a-014 figure 15. shutdown current vs. temperature
ad5245 rev. a | page 10 of 20 code (decimal) ?50 0 50 100 150 200 32 096 64 128 160 192 224 256 rheostat mode tempco (ppm/c) 03436-a-015 figure 16. rheostat mode tempco ?r wb /?t vs. code code (decimal) ?20 0 20 40 60 80 100 120 140 160 32 096 64 128 160 192 224 256 potentiometer mode tempco (ppm/c) 03436-a-016 figure 17. potentiometer mode tempco ?v wb /?t vs. code 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 1 000 000.000hz mag (a/r) ?8.918db start 1 000.000hz stop 1 000 000.000hz 03436-a-017 figure 18. gain vs. frequency vs. code, r ab = 5 k? 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 510 634.725hz mag (a/r) ?9.049db start 1 000.000hz stop 1 000 000.000hz 03436-a-018 figure 19. gain vs. frequency vs. code, r ab = 10 k? 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 100 885.289hz mag (a/r) ?9.014db start 1 000.000hz stop 1 000 000.000hz 03436-a-019 figure 20. gain vs. frequency vs. code, r ab = 50 k? 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 54 089.173hz mag (a/r) ?9.052db start 1 000.000hz stop 1 000 000.000hz 03436-a-020 figure 21. gain vs. frequency vs. code, r ab = 100 k?
ad5245 rev. a | page 11 of 20 10k 100k 1m 10m ?5.5 ?6.0 ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 ?9.0 ?9.5 ? 10.0 ? 10.5 ref level ?5.000db /div 0.500db start 1 000.000hz stop 1 000 000.000hz r = 5k ? r = 10k ? r = 50k ? r = 100k ? 5k ? ? 1.026mhz 10k ? ? 511khz 50k ? ? 101khz 100k ? ? 54khz 03436-a-021 figure 22. C3 db bandwidth @ code = 0x80 frequency (hz) 10k 100 100k 1m 1k 0 20 40 60 psrr (?db) code = 0x80, v a = v dd , v b = 0v psrr @ v dd = 3v dc 10% p-p ac psrr @ v dd = 5v dc 10% p-p ac 03436-a-022 figure 23. psrr vs. frequency i dd ( a) frequency (hz) 10k 800 700 600 500 400 300 900 200 100 100k 1m 10m 0 code = 0x55 code = 0xff v dd = 5v 03436-a-023 figure 24. i dd vs. frequency vw scl ch 1 5.00v b w ch 2 5.00 v b w m 200ns a ch1 3.00 v 1 2 v a = 5v v b = 0v 03436-a-026 figure 25. large signal settling time, code 0xffC>0x00 vw scl ch 1 200mv b w ch 2 5.00 v b w m 100ns a ch2 3.00 v 1 2 03436-a-024 figure 26. digital feedthrough vw scl ch 1 100mv b w ch 2 5.00 v b w m 200ns a ch1 152mv 1 2 v a = 5v v b = 0v 03436-a-025 figure 27. midscale glitch, code 0x80C>0x7f
ad5245 rev. a | page 12 of 20 test circuits figure 28 to figure 34 illustrate the test circuits that define the test conditions used in the product specification tables. v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n 03436-a-027 figure 28. test circuit for potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut 03436-a-028 figure 29. test circuit for resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w 03436-a-029 figure 30. test circuit for wiper resistance 03436-a-030 ? v ms % dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log ms dd ( ) v dd v a v ms a w b v+ ? v ? v ? v figure 31. test circuit for power supply sensitivity (pss, pssr) +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in 03436-a-031 figure 32. test circuit for gain vs. frequency w b gnd to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v 03436-a-032 figure 33. test circuit for incremental on resistance w b v cm i cm a nc gnd nc v dd dut nc = no connect 03436-a-033 figure 34. test circuit for common-mode leakage current
ad5245 rev. a | page 13 of 20 theory of operation the ad5245 is a 256-position digitally controlled variable resistor (vr) device. an internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b is available in 5 k?, 10 k?, 50 k?, and 100 k?. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. a w b a w b a w b 03436-a-034 figure 35. rheostat mode configuration assuming that a 10 k? part is used, the wipers first connection starts at the b terminal for data 0x00. because there is a 50 ? wiper contact resistance, such a connection yields a minimum of 100 ? (2 50 ?) resistance between terminals w and b. the second connection is the first tap point, which corresponds to 139 ? (r wb = r ab /256 + 2 r w = 39 ? + 2 50 ?) for data 0x01. the third connection is the next tap point, representing 178 ? (2 39 ? + 2 50 ?) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 ? (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 03436-a-035 figure 36. ad5245 equivalent rdac circuit the general equation determining the digitally programmed output resistance between w and b is w ab wb r r d d r + = 2 256 ) ( (1) where: d is the decimal equivalent of th e binary code loaded in the 8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 10 k? and the a terminal is open circuited, the following output resistance r wb is set for the indicated rdac latch codes. table 6. codes and corresponding r wb resistance d (dec.) r wb (?) output state 255 9,961 full scale (r ab C 1 lsb + r w ) 128 5,060 midscale 1 139 1 lsb 0 100 zero scale (wiper contact resistance) note that, in the zero-scale condition, a finite wiper resistance of 100 ? is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa r r d d r + ? = 2 256 256 ) ( (2) for r ab = 10 k? and the b terminal open circuited, the following output resistance r wa is set for the indicated rdac latch codes. table 7. codes and corresponding r wa resistance d (dec.) r wa (?) output state 255 139 full scale 128 5,060 midscale 1 9,961 1 lsb 0 10,060 zero scale
ad5245 rev. a | page 14 of 20 typical device-to-device matching is process lot dependent and may vary by up to 30%. since the resistance element is processed in thin film technology, the change in r ab with temperature has a very low 45 ppm/c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper-to-b and wiper-to-a proportional to the input voltage at a to b. unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a v i w b v o 03436-a-036 figure 37. potentiometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper-to-b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the volt- age applied across terminal ab divided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is b a w v d v d d v 256 256 256 ) ( ? + = (3) a more accurate calculation, which includes the effect of wiper resistance, v w , is b ab wa a ab wb w v r d r v r d r d v ) ( ) ( ) ( + = (4) operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb and not the absolute values. therefore, the temperature drift reduces to 15 ppm/c. esd protection all digital inputs are protected with a series of input resistors and parallel zener esd structures, shown in figure 38 and figure 39. this applies to the digital input pins sda, scl, and ad0. logic 340 ? gnd 03436-a-037 figure 38. esd protection of digital pins a, b, w gnd 03436-a-038 figure 39. esd protection of resistor terminals terminal voltage operating range the ad5245 v dd and gnd power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. supply signals present on terminals a, b, and w that exceed v dd or gnd are clamped by the internal forward-biased diodes (see figure 40). gnd a w b v dd 03436-a-039 figure 40. maximum terminal voltages set by v dd and gnd power-up sequence because the esd protection diodes limit the voltage compliance at terminals a, b, and w (see figure 40), it is important to power v dd /gnd before applying any voltage to terminals a, b, and w; otherwise, the diode is forward biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ideal power-up sequence is in the following order: gnd, v dd , digital inputs, and then v a , v b , and v w . the relative order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd /gnd.
ad5245 rev. a | page 15 of 20 layout and power supply bypassing it is good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 41). note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. v dd gnd v dd c3 10 f c1 0.1 f ad5245 + 03436-a-040 figure 41. power supply bypassing constant bias to retain resistance setting for users who desire nonvolatility but cannot justify the additional cost for the eemem , the ad5245 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. the ad5245 is designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. the graph in figure 42 demonstrates the power consumption from a 3.4 v 450 ma-hr li-ion cell phone battery, which is connected to the ad5245. the measurement over time shows that the device draws approximately 1.3 a and consumes negligible power. over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. days battery life depleted 0 90% 92% 94% 96% 51015 98% 100% 102% 104% 106% 108% 110% 20 25 30 t a = 25 c 03436-a-041 figure 42. battery operating life depletion this demonstrates that constantly biasing the potentiometer is not an impractical approach. most portable devices do not require the removal of batteries for the purpose of charging. although the resistance settin g of the ad5245 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the ad5245. if and when total power is lost, the user should be provided with a means to adjust the setting accordingly. evaluation board an evaluation board, along with all necessary software, is available to program the ad5245 from any pc running windows? 98/2000/xp. the graphical user interface, as shown in figure 43, is straightforward and easy to use. more detailed information is available in the user manual, which comes with the board. 03436-a-042 figure 43. ad5245 evaluation board software the ad5245 starts at midscale upon power-up. to increment or decrement the resistance, the user may simply move the scroll- bars on the left. to write any specific value, the user should use the bit pattern in the upper screen and click on the run button. the format of writing data to the device is shown in table 8. to read the data out from the device, the user can simply click on the read button. the format of the read bits is shown in table 9.
ad5245 rev. a | page 16 of 20 i 2 c interface i 2 c compatible 2-wire serial bus the 2-wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 45). the following byte is the slave address byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5245 has one configurable address bit, ad0 (see table 8). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. on the other hand, if the r/ w bit is low, the master writes to the slave device. 2. in write mode, the second byte is the instruction byte. the first bit (msb) of the instruction byte is a dont care. the second msb, rs, is the midscale reset. a logic high on this bit moves the wiper to the center tap where r wa = r wb . this feature effectively writes over the contents of the register, and thus, when taken out of reset mode, the rdac remains at midscale. the third msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. also, during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the remainder of the bits in the instruction byte are dont cares (see table 8). 3. after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 45). 4. in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with write mode, eight data bits are followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46). 5. after all data bits have been read or written, a stop condi- tion is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the tenth clock pulse to establish a stop condition (see figure 45). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the tenth clock pulse, which goes high to establish a stop condition (see figure 46). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output updates on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5245 rev. a | page 17 of 20 table 8 . write mode s 0 1 0 1 1 0 ad0 w a x rs sd x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 9. read mode s 0 1 0 1 1 0 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte s = start condition p = stop condition a = acknowledge x = dont care w = write r = read rs = reset wiper to midscale 0x80 sd = shutdown connects wiper to b terminal and open circuits a terminal. it does not change contents of wiper register. d7, d6, d5, d4, d3, d2, d1, d0 = data bits t 1 t 3 t 4 t 2 t 7 t 8 t 9 ps p s t 10 t 5 t 9 t 8 scl sd a t 2 t 6 03436-a-043 figure 44. i 2 c interface detailed timing diagram scl frame 1 frame 2 start b y master ack by ad5245 slave address byte stop by master instruction byte sda 0 1 0 1 1 0 ad0 r/w xrs x x x x x 1 9 19 d7 d6 d5 d4 d3 d2 d1 d0 ack by ad5245 frame 3 data byte 1 9 ack by ad5245 sd 03436-a-044 figure 45 . writing to the rdac register no ack by master scl sda 0 1 0 1 1 0 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 frame 1 frame 2 start by master ack by ad5245 slave address byte rdac register stop by master 03436-a-045 figure 46. reading data from a previously selected rdac register in write mode
ad5245 rev. a | page 18 of 20 multiple devices on one bus figure 47 shows two ad5245 devices on the same serial bus. each has a different slave address because the states of their ad0 pins are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c compatible interface. master ad5245 sda scl r p r p +5v +5v sda scl sda scl ad5245 ad0 ad0 03436-a-046 figure 47. multiple ad5245 devices on one i 2 c bus
ad5245 rev. a | page 19 of 20 outline dimensions 1 3 5 6 2 8 4 7 2.90 bsc pin 1 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc compliant to jedec standards mo-178ba figure 48. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters ordering guide model temperature package description package option branding code r ab (?) full container quantity ad5245brj5-r2 C40c to +125c sot-23 rj-8 d0g 5 k 250 ad5245brj5-rl7 C40c to +125c sot-23 rj-8 d0g 5 k 3,000 ad5245brjz5-r2 1 C40c to +125c sot-23 rj-8 d0g 5 k 250 ad5245brjz5-rl7 1 C40c to +125c sot-23 rj-8 d0g 5 k 3,000 AD5245BRJ10-R2 C40c to +125c sot-23 rj-8 d0h 10 k 250 ad5245brj10-rl7 C40c to +125c sot-23 rj-8 d0h 10 k 3,000 ad5245brjz10-r2 1 C40c to +125c sot-23 rj-8 d0h 10 k 250 ad5245brjz10-rl7 1 C40c to +125c sot-23 rj-8 d0h 10 k 3,000 ad5245brj50-r2 C40c to +125c sot-23 rj-8 d0j 50 k 250 ad5245brj50-rl7 C40c to +125c sot-23 rj-8 d0j 50 k 3,000 ad5245brjz50-r2 1 C40c to +125c sot-23 rj-8 d0j 50 k 250 ad5245brjz50-rl7 1 C40c to +125c sot-23 rj-8 d0j 50 k 3,000 ad5245brj100-r2 C40c to +125c sot-23 rj-8 d0k 100 k 250 ad5245brj100-rl7 C40c to +125c sot-23 rj-8 d0k 100 k 3,000 ad5245brjz100-r2 1 C40c to +125c sot-23 rj-8 d0k 100 k 250 ad5245brjz100-rl7 1 C40c to +125c sot-23 rj-8 d0k 100 k 3,000 ad5245eval 2 evaluation board 1 z = pb-free part. 2 the evaluation board is shipped with the 10 k? r ab resistor option; however, the board is compatible with all available resistor value options.
ad5245 rev. a | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c03436C0C3/04(a)

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